Memory controllers in FPGAs are the bane of my existence, help needed
I want to put together a softcore 68K computer system, just something simple.
I’ve purchased, but not yet received, the Terasic Cyclone V GX Starter Kit, an Altera FPGA eval board.
It looks pretty sweet and includes some fun stuff I’ve never done like HDMI connectors, has some easy to access onboard SRAM, has built in FTDI USB support, built in programmer, built-in flash for non-volatile storage, 77K logic elements, and the list goes on. Looks like a really sweet board EXCEPT for one line on the datasheet:
4Gb LPDDR2 x32 bits data bus
“Oh no! Not yet a different memory chip or interface”
What’s nice is that there are (2) HARD memory controllers built-in to the FPGA, and so you don’t have to waste logic elements for defining your own. While I’m not sure what I was thinking, I really expected the interface to the memory to be very simple…. You know something like a FIFO-front end where you’d specific address, read/write, data, and then throw some read_data_valid switch and voila. Well, of course, I’m wrong.
Again, I’m in the middle of a memory controller nightmare.
For my Altera DE0, I modified the memory controller found here. It works like a champ, and the interface is pretty darn simple.
I could really use some help putting together a simple to use DDR2 controller to access this chip:
It’s configured like this: 16 Meg x 32 x 8 banks x 1 die. Rows are addressed like this “16K (A[13:0])” and columns “1K (A[9:0])” using Single Channel Addressing. Cycle Time is “-25 = 2.5ns, tCK RL = 6″
What I don’t know is whether I can even start with a SDRAM controller and then expand on that, or if a completely different approach is warranted. I know that DDR2 is still SDRAM, and the interface to the new memory chip is very similar. I don’t really need the double-pumping or the increased data rate — I’d take anything to get off the ground.
Ideally, I’d find a verilog module for a controller with an example module that instantiates it, writes to some addresses, and then reads them back and verifies them.
A google search, as well as investigation on OpenCores hasn’t yielded much. This Altera youtube video is promising, but it stopped short on showing the HDL-specific details on how to instantiate it, and how to actually USE the module that gets created. This is assuming that everything goes swimmingly during the fairly complicated MegaWizard process.
If you’ve got any experience or helpful tips, I’d appreciate it.