Some reverse engineering notes on DataFlyer 500 BUSS Pal
As you may have seen in this other post here I have an interest in this Amiga hard drive controller designed for the Commodore Amiga 500. I used this for years to interface an HDD. At the time I took some photos of the PCB and shared some my notes, I also dumped the Boot ROM from the board, which had already been done previously — and compared it. I did it both as an exercise to play with this stuff, but also to see if mine differed from existing sources, which it did not.
The rest of the board has fairly off-the-shelf 74 logic chips which are called out in that other post, along with the main chip being the AM5380 SCSI IC on the PCB.
One piece of engineering, though, that I assume is custom to Expansion Systems was their PAL. I don’t know what its main function is, but I’m starting to collect information to the form the picture. When these type of chips die, you don’t just go on digikey or mouser and get a new one. So understanding how they work and “backing up” what they do precisely helps preserve these things for the future.
These notes are raw and unrefined, but Bob reminded me that there’s very little specific information about this PAL anywhere on the internet, and thought I’d share.
This exercise was important to determine how the inputs and outputs are being used to determine the optimal dumping strategy.
Pin connections for the TIBPAL16L8-25CN labeled BUSS on the DataFlyer 500 SCSI-only version.
Pins 1-9, and 11 are input-only on the PAL
These inputs are driven by
PAL Pin Numbers
Notes on what’s connected
Pin 1
the output from the SN74F32N OR gate chip Pin 8(called 3Y). There’s an OR function between pins 3A and 3B (pins 9 and 10 on that chip) — and output on 3Y(PIN 8). These are driven by the 68000 _FC (Function Code) processor status pins bits 0 and 1. No clue why they’d need or want access to these signals. Card edge connector pins 31 and 33.
Pin 2
card edge connector pin 10. This is +12v from the Amiga and I have no clue why they’d drive 12volts into this.
Pin 3
27C256 ROM pin 8. Address line A2
Pin 4
27C256 ROM pin 7. Address line A3
Pin 5
27C256 ROM pin 6. Address line A4
Pin 6
27C256 ROM pin 5. Address line A5
Pin 7
card edge connector pin 68 from Amiga. Bidirectional R_W pin.
Pin 8
card edge connector pin 45 from Amiga. Pin from Amiga Address bus. 8th bit from a 23:1 grouping. Not sure counting which direction.
Pin 9
card edge connector pin 72 from Amiga. Active low _UDS. Upper data select. High order byte matters.
Pin 10
Ground
Pin 11
card edge connector pin pin 55 from Amiga. Bidirectional _HLT pin. Active low
Pin 12
output only pin and drives the active low chip enable pin on 27C256 ROM pin 20. Input on ROM
Pins 13 through 18 are I/O pins and can be either depending on programming/configuration
PAL Pin Numbers
Notes on what’s connected
Pin 13
card edge connector pin 16 to Amiga. Active low _CCK. Output by Amiga. Pin must be used as an input pin on the PAL.
Pin 14
connected to 74LS373 chip pin 11 latch enable active high. Input on 373.
Pin 15
connected to AM5380PC chip pin 24 I/O READ active low. Input on the 5380.
Pin 16
connected to AM5380PC chip pin 28 RESET active low. Input on the 5380.
Pin 17
connected to AM5380PC chip pin 26 DATA ACKNOWLEDGE active low. Input on the 5380.
Pin 18
connected to 74LS373 chip pin 1 OUTPUT ENABLE active low. Input on 373.
Pin 19
output only pin. connected to AM5380PC chip pin 21 CHIP SELECT active low. Input on the 5380.
Pin 20
VCC +5v
Something to remember is that these notes are not gospel and subject to mistakes, misunderstandings, and incomplete thoughts. The pins are also connected to MULTIPLE THINGS. In many cases, I’m listing just one of them. The signal may not originate from that device, but instead be a consumer of that signal.
Next steps: Determine if I can simply start stimulating the inputs on this chip with a microcontroller GPIO pin, and then capture the 7 output bits.