Below is a label diagram of how the PCB is handling a read from the Amiga. (and partial theory of operation here too). As of 1/18/14, Schematics are coming.

1. There’s a falling edge of /RAS that occurs. At this moment, we latch the row address that’s on the multiplexed bus. All 9 nine pins.
2. Next, we see the two /CASs drop. This indicates that it’s a WORD being read, instead of just a single BYTE. If it was a BYTE read, we’d see only a single /CAS drop. Yellow Line.
3. Here we see the reaction of the glue logic detecting one of the /CAS’s dropped. It happens so fast, that my logic analyzer sees it as almost simultaneous(also Yellow Line). It happens in less than 3ns and is the propagation of a single NAND gate in a 74ACT00. It’s at that point that we latch the column address that’s on the bus. We must ensure that the time between (5) and (6) is enough, because the address bus needs to be fully settled from the propagation of the latch before we tell the SRAM to read. This is called the data setup time, and on the SRAM, the requirement happens to be 0ns. This means that as long as the bus is settled by the time that /CE is asserted to the SRAM, we are ok.
4. Next, we check to see if /RAS was asserted at the same time, and if so, it’s GO TIME to command the SRAM to read. I purposely slow down the propagation of the combined P2 and P3 signals to make P4 by using slower logic (74LS instead of 74ACT). Purple Line.
5. The bus settles by the time we get to the Green line.
6. /CE is asserted, and the SRAM will be performing the read operation, and placing the results on the Amiga’s 16-bit databus. The 373′s within the Amiga will latch this data, and forward it to the 68000. Brown Found line.

Some notable things, as you can see in the measurement markers M1, M2, and M3 at the top of the image.

• Our access time from the falling edge of CAS to actually delivering the data is about 21ns. This is pretty impressive, I think. The original dram chips on the Rev5 motherboard and the Rev5 A501 are 120ns. Smokin’.
• While I said that the time between (5) and (6) has to be enough, which is true, this also implies that there’s enough time between (3) and (6) for the latch to propagate.
• This diagram covers the OUTPUT of the latches, so at no time (on this diagram) do we actually see the multiplexed bus.
• The timing margin and the “key spec” for this PCB is between (5) and (6), and we have plenty of time: around 9 or 10ns. I took a ton of measurements, and they all fall between 9ns on the short side with 12ns-15ns being typical. This clearly meets the required 0ns data setup time on the SRAM chip.
• Every other timing requirement is CLEARLY and EASILY met.